1. Field of the Invention
The present invention relates to designing and manufacturing a clock distribution network in an integrated circuit.
2. Discussion of the Related Art
In high speed digital design, distributing and managing a system clock presents real challenges. The term “clock skew” is used to denote the tolerance or uncertainty in the arrival time of the active clock edge at state devices due to variation in the propagation delay in the paths of the clock distribution network. Tiny differences in propagation delay over clock traces in a complex digital product often lead to unacceptable degradations in overall system timing margins. This is controlled in current systems using clock drivers or buffers (referred to herein as clock tree cells) which provide one common clock input and a plurality of ganged outputs, These clock tree cells are arranged in a “tree” clock distribution topology, where each cell feeds cells at the next level of the tree or a set of loads at the end of the tree. Loads can be registers implemented as flip-flops (herein flops) or gates. To minimize skew-related issues, delays of all clock traces should be balanced. In system-on-chip (SOC) designs using multi-level clock trees, the worst case skew needs to be controlled between any of the branch nodes. Wherever the path between two branch nodes traverses a clock tree cell input, the input-to-output skew specification for that cell enters the overall skew equation for the chip. The concept of active use of clock skew, or useful skew, has been used to allow overall timing on the chip to be controlled by appropriately selecting clock tree cells, for example to maximize performance of the system or assist in timing closure. For example, where a flop driven by a clock has tight timing to one side and relaxed timing on the other, a tool can try to move the clock edge toward the relaxed side by altering the size of clock tree cells and changing clock branching points. However, it can be a complex issue to optimize system behavior by adjusting skew behavior due to the limitation of existing tools.
One existing technique for using active clock skew is integrated with a clock tree synthesis (CTS) tool. That is, as the clock tree is synthesized, the drive strength of clock tree cells and the location of branch points are adjusted to improve the overall timing of the integrated circuit. However, because the technique is applied before the detailed routing of the design is established, the results can be sub-optimal.
Another technique is to manually adjust clock skew after routing of the design has been completed. This has the advantage that it is based on accurate data from the integrated circuit because it uses the results of a timing analysis tool including parasitic data. However, it is a manually intensive process. Moreover, changes which would require clock tree cells to be upsized may not be possible without disturbing other circuits within the integrated circuit.